UART Protocol Exerciser and Analyzer

UART Protocol Analyzer (PGY-UART-EX-PD) is the Protocol Analyzer with multiple features to capture and debug communication between the host and the design under test. PGY-UART-EX-PD is the leading instrument that enables the design and test engineers to test the respective UART designs for its specifications by configuring the PGY-UART-EX-PD as Master/Slave, generating UART traffic and decoding the UART protocol decode packets.

UART stands for Universal Asynchronous Receiver Transmitter. A UART’s main purpose is to transmit and receive serial data. PGY-UART-EX-PD is the leading instrument that enables the design and test engineers to test the UART designs for its specifications. Generating UART traffic with custom traffic capability and decoding UART Protocol packets.
 

Key features

• Supports custom UART traffic generation
• Simultaneously generate UART traffic and Protocol decode of the bus
• Variable UART baud rates
• Continuous streaming of protocol data to the host computer to provide a large buffer
• A timing diagram of the Protocol decoded bus
• Listing view of Protocol activity
• Error Analysis in Protocol Decode
• Ability to write exerciser script to combine multiple data frame generation at different data speeds
• USB 2.0/3.0 host computer interface
• API support for automation in Python or C++