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74LS623N
74LS623N

 

74LS623N

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DCTAL BUS TRANSCEIVERS

Below is the parameter table and instructions for the 74LS623N, which is a Dual 4-bit Binary/BCD Up/Down Counter with Preset and Clock Inhibit.

74LS623N Parameter Table

Parameter Symbol Min Typical Max Unit
Supply Voltage VCC 4.75 5.0 5.25 V
Input Low Voltage VIL 0.8 - - V
Input High Voltage VIH - - 2.0 V
Output Low Voltage VOL 0.4 - - V
Output High Voltage VOH - - 2.4 V
Propagation Delay Time (Low to High) tPLH 15 - 25 ns
Propagation Delay Time (High to Low) tPHL 15 - 25 ns
Power Dissipation PD - 150 - mW
Operating Temperature Range TA 0 - 70 °C

Instructions for 74LS623N

Pin Configuration

Pin Number Pin Name Description
1 QA1 Counter A Bit 0 Output
2 QB1 Counter A Bit 1 Output
3 QC1 Counter A Bit 2 Output
4 QD1 Counter A Bit 3 Output
5 MR1 Master Reset for Counter A
6 CP1 Clock Pulse for Counter A
7 GND Ground
8 LD1 Load Control for Counter A
9 D1A Data Input for Counter A Bit 0
10 D1B Data Input for Counter A Bit 1
11 D1C Data Input for Counter A Bit 2
12 D1D Data Input for Counter A Bit 3
13 CI1 Clock Inhibit for Counter A
14 QA2 Counter B Bit 0 Output
15 QB2 Counter B Bit 1 Output
16 QC2 Counter B Bit 2 Output
17 QD2 Counter B Bit 3 Output
18 MR2 Master Reset for Counter B
19 CP2 Clock Pulse for Counter B
20 VCC Power Supply
21 LD2 Load Control for Counter B
22 D2A Data Input for Counter B Bit 0
23 D2B Data Input for Counter B Bit 1
24 D2C Data Input for Counter B Bit 2
25 D2D Data Input for Counter B Bit 3
26 CI2 Clock Inhibit for Counter B

Functional Description

  1. Clock Pulse (CP): The clock pulse input (CP1 and CP2) controls the counting operation. The counter increments or decrements on the rising edge of the clock pulse.
  2. Master Reset (MR): The master reset input (MR1 and MR2) resets the counter to 0 when high.
  3. Load Control (LD): The load control input (LD1 and LD2) loads the data from the data inputs (D1A-D1D and D2A-D2D) into the counter when high.
  4. Clock Inhibit (CI): The clock inhibit input (CI1 and CI2) prevents the counter from responding to the clock pulse when high.
  5. Data Inputs (D1A-D1D, D2A-D2D): These inputs provide the data to be loaded into the counter when the load control is active.
  6. Outputs (QA1-QD1, QA2-QD2): These outputs provide the current count value of the counter.

Operating Modes

Example Application

  1. Connect VCC to +5V and GND to ground.
  2. Connect the clock pulse (CP1 and CP2) to your clock source.
  3. Set the load control (LD1 and LD2) low to enable counting.
  4. Set the clock inhibit (CI1 and CI2) low to allow the counter to respond to the clock.
  5. Set the master reset (MR1 and MR2) low to prevent resetting.
  6. Observe the outputs (QA1-QD1, QA2-QD2) to monitor the count.

This should cover the essential parameters and instructions for using the 74LS623N dual 4-bit binary/BCD up/down counter.

(For reference only)

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