74LS173: Top Choice in United States (USA) Utsource Holding Company Limited

Description

BUY 74LS173 https://www.utsource.net/itm/p/98261.html
4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

Below is the parameter table and instructions for the 74LS173 Quad D-Type Flip-Flop with Clear and Preset.

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage	V_CC	4.75	5.0	5.25	V
Output High Voltage	V_OH	-	2.4	3.4	V
Output Low Voltage	V_OL	0.0	0.4	0.5	V
Input High Voltage	V_IH	2.0	-	-	V
Input Low Voltage	V_IL	0.8	-	-	V
Input Current (High)	I_IH	-	20	40	μA
Input Current (Low)	I_IL	-	-1.6	-0.4	mA
Output Current (Source)	I_OH	-	0.4	4.0	mA
Output Current (Sink)	I_OL	-	-8.0	-4.0	mA
Propagation Delay Time	t_pd	15	22	35	ns
Clear to Q Time	t_pcq	15	22	35	ns
Preset to Q Time	t_ppq	15	22	35	ns
Setup Time	t_su	20	-	-	ns
Hold Time	t_h	5	-	-	ns
Power Dissipation	P_D	-	150	-	mW

Clock Input (CLK):
- The flip-flop captures the data at the D input on the rising edge of the clock signal.
Preset (PR?):
- When PR? is low, the corresponding Q output is set to high regardless of the clock or data inputs.
Clear (CLR?):
- When CLR? is low, the corresponding Q output is set to low regardless of the clock or data inputs.
Output Enable (OE?):
- When OE? is low, the outputs are enabled. When OE? is high, the outputs are in a high-impedance state.

Setup Time (t_su): The data must be stable before the rising edge of the clock.
Hold Time (t_h): The data must remain stable after the rising edge of the clock.
Propagation Delay (t_pd): The time it takes for the output to change after the rising edge of the clock.

Synchronous Counter: Use multiple 74LS173 chips to create a synchronous counter by cascading the clock and data inputs.
Data Latching: Use the chip to latch data from a bus into a register.

This information should help you understand and use the 74LS173 effectively in your circuits.

(For reference only)