BUY 74HC597AP https://www.utsource.net/itm/p/98040.html
8-BIT LATCH/SHIFT REGISTER
Description: The 74HC597AP is a high-speed Si-gate CMOS device and is pin compatible with the low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A.
Features:
High speed: tPD = 11 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 μA (max) at Ta = 25 °C
High noise immunity: VNIH = VNIL = 28 % VCC (min)
Balanced propagation delays: tPLH tPHL
Wide operating voltage range: VCC (opr) = 2 V to 6 V
Pin and function compatible with 74LS597
Complies with JEDEC standard no. 7A
Applications:
Data acquisition systems
High speed line receivers
High speed line drivers
High speed clock distribution
High speed bus transceivers
High speed address multiplexers
High speed data multiplexers
(For reference only)
