BUY 74LS112 https://www.utsource.net/itm/p/1725349.html
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The 74LS112 is a dual J-K flip-flop with reset integrated circuit manufactured by Motorola. It is part of the 74LS family of logic ICs. Description: The 74LS112 contains two J-K flip-flops with reset. Each flip-flop has two inputs, J and K, and two outputs, Q and Q. The reset input is active low and will reset the outputs to a low state. The flip-flops are edge-triggered, meaning that the outputs will change state on the rising edge of the clock pulse. Features: Dual J-K flip-flops with reset Edge-triggered Active low reset Low power consumption Available in DIP-16 package Applications: Counters Shift registers Frequency dividers Timers State machines
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