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Reference Design kit for ADNS-5020
| Parameter |
Description |
Value |
| Device Type |
Decade Counter with Reset and Clock Inhibit |
SN74LS160N |
| Function |
4-bit Binary Counter |
|
| Logic Family |
LS (Low-power Schottky) |
|
| Supply Voltage (Vcc) |
Operating voltage |
4.75 V to 5.25 V |
| Propagation Delay Time |
Typical propagation delay time at Vcc = 5V |
19 ns |
| Power Consumption |
Maximum power consumption at TA = 25°C |
83 mW |
| Operating Temperature |
Industrial temperature range |
-40°C to +85°C |
| Package Type |
DIP, SOIC |
|
| Pin Count |
Number of pins |
16 |
Instructions for Use:
Power Supply Connections:
- Connect pin 16 (Vcc) to the positive supply voltage (typically 5V).
- Connect pin 8 (GND) to the ground.
Clock Input (CP):
- Connect the clock signal to pin 10 (CP). The counter advances on the rising edge of the clock pulse.
Reset Function (MR):
- Pin 1 (MR) is the master reset input. Apply a high signal to this pin to reset the counter to 0000.
Clock Inhibit (ENT):
- Pin 2 (ENT) is the enable T input. When low, it inhibits counting regardless of the state of ENP.
Enable Pulse (ENP):
- Pin 3 (ENP) is the enable P input. Both ENP and ENT must be high for counting to occur.
Output Pins (QA-QD):
- The binary outputs QA (pin 7), QB (pin 1), QC (pin 2), and QD (pin 6) represent the 4-bit count from 0000 to 1001 (decimal 0-9).
Carry Output (RCO):
- Pin 9 (RCO) goes high when the count reaches 1001 (decimal 9) and can be used to cascade multiple counters.
Handling Care:
- Ensure all unused inputs are tied to either Vcc or GND to prevent floating states which can lead to unpredictable behavior.
- Avoid exceeding the maximum ratings specified in the datasheet to prevent damage to the device.
(For reference only)
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